 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| U2730B-N Improved L-Band Down-Converter for DAB Receivers Description The U2730B-N is a monolithically integrated L-band down-converter circuit fabricated in TEMIC Semiconductors' advanced UHF5S technology. This IC is an improved version of the U2730B-B and covers all functions of an L-band downconverter in a DAB receiver. The device includes a gain controlled amplifier, a gain controlled mixer, an output buffer, a gain control block, a power save function for the analog part, an L-band oscillator and a complete frequency syntheziser unit. The frequency syntheziser block consists of a reference oscillator/ buffer, a reference divider, a RF divider, a tristate phase detector, a loop filter amplifier, a lock detector, a programmable charge pump, a test interface and a control interface. Electrostatic sensitive device. Observe precautions for handling. Features D Supply voltage: 8.5 V D RF frequency range: 1400 MHz to 1550 MHz D IF frequency range: 150 MHz to 250 MHz D Enhanced IM3 rejection D Overall gain control range: typ. 30 dB D DSB noise figure: 9.5 dB D Gain-controlled amplifier and L-band mixer D Power-down function for the analog part D On-chip gain-control circuitry D On-chip VCO, typical frequency 1261.568 MHz D Internal VCO can be overdriven by an external LO D On-chip frequency synthesizer - Fixed LO divider factor: 2464 - Nine reference divider factors selectable: 32, 33, 35, 36, 48, 49, 63, 64, 65 - A reference oscillator (can be overdriven by an external reference signal - - - - Tristate phase detector with programmable charge pump De-activation of tuning output programmable Lock-status indication Test interface VCC2 9 Voltage stabilizer Block Diagram TH 17 AGC 18 U Analog part RF NRF TANK VREF 26 25 5 4 Power save (analog part) Power down Test interface Control interface Bandgap Lock detector IF 19 VCC1 VCC3 VCC4 3 20 28 GND 6, 7, 8, 21, 22, 23, 24 Internal 5 V supply voltage for frequency synthesizer 14 PLCK 20k VCO RF counter : 2464 Tristate phase detector Charge pump (200u/ 300u) 12 CD Reference counter : Nref 13 PD 1 PSM 15 OSCB 16 OSCE 11 TI 10 27 2 CI SI1 SI2 Figure 1. Block diagram Rev.A1, 10-Jul-00 1 (13) Preliminary Information U2730B-N Ordering Information Extended Type Number U2730B-NFS U2730B-NFSG1 Package SSO28 SSO28 Tube Taped and reeled according to IEC 286-3 Remarks Pin Description PSM SI2 VCC1 VREF TANK GND GND GND VCC2 28 VCC4 27 SI1 26 RF 25 NRF 24 GND 23 GND 22 GND 21 GND 20 VCC3 19 IF 18 AGC 17 TH 16 OSCE 15 OSCB Pin 1 2 3 4 5 4 5 6 7 8 9 6, 7, 8, 21, 22, 23, 24 9 10 11 12 13 14 15 16 17 18 Symbol PSM SI2 VCC1 VREF TANK GND Function Power save mode Control input Supply voltage VCO Reference pin of VCO Tank pin of VCO Ground 1 2 3 VCC2 CI TI CD PD PLCK OSCB OSCE TH AGC Supply voltage PLL Control input Test interface Active filter output Tristate charge pump output Lock-indication output (open collector) Input of internal oscillator/ buffer Output of internal oscillator/ buffer Threshold voltage of comparator Charge-pump output of comparator, AGC input for amplifier and mixer Intermediate frequency output Supply voltage RF input (inverted) RF input Control input Supply voltage CI 10 TI 11 CD 12 PD 13 PLCK 14 19 20 25 26 27 IF VCC3 NRF RF SI1 VCC4 Figure 2. Pinning 28 Functional Description The U2730B-N is an L-band down-converter circuit covering a gain controlled amplifier, a gain controlled mixer, an output buffer, a gain control circuitry, an L-band oscil- lator and a frequency synthesizer block. Designed for applications in an DAB receiver the purpose of this circuit is to down-convert incoming L-band signals in the frequency range between 1452 MHz and 1492 MHz to an IF frequency in the range between about 190 MHz and 2 (13) Rev.A1, 10-Jul-00 Preliminary Information U2730B-N 230 MHz which can be handled by a subsequent DAB tuner. A block diagram of this circuit is shown in figure 1. A main different to the U2730B is an enhanced IM3 rejection. By varying the value of resistor RTH a power threshold between about -33 dBm and -20 dBm at IF- port can be selected. Voltage-Controlled Oscillator A voltage-controlled oscillator supplies an LO signal to the mixer. An equivalent circuit of this oscillator is shown in figure 7. In the application circuits figures 7 and 8, a ceramic coaxial resonator is applied to the oscillator's Pins TANK and VREF. It should be noted that the Pin REF has to be blocked carefully. Figure 8 shows a different application where the oscillator is overdriven by an external oscillator. In any case, a DC path at a low impedance must be established between the Pins TANK and VREF. The output signal of the oscillator is fed to the LO divider block of the frequency synthesizer unit which locks the VCO's frequency on the frequency of a reference oscillator. Figure 12 shows the typical phase-noise performance of the oscillator in locked state. Gain-Controlled Amplifier RF signals applied to the input Pin `RF' are amplified by a gain-controlled amplifier. The complementary Pin NRF is not internally blocked, it is recommended to block this pin carefully by an external capacitor. The gain-control voltage is generated by an internal gain-control circuitry. The output signal of this amplifier is fed to a gain-controlled mixer. Gain-Controlled Mixer and Output Buffer The purpose of this mixer is to down-convert the L-band signal in the frequency range of 1452 MHz to 1492 MHz to an IF frequency in the range of about 190 MHz to 230 MHz. Like the amplifier, the gain of the mixer is controlled by the gain-control circuitry. The IF signal is buffered and filtered by a one-pole lowpass filter at a 3-dB frequency of about 500 MHz and then it is fed to the single-ended output Pin IF. Overall Properties of the Signal Path The overall gain of this circuit amounts 24 dB, the gaincontrol range is about 30 dB. With a new AGC-concept in the amplifier and mixer the U2730B-N reach better intermodulation distance (DIM3) at higher IF output power levels. Power Save Mode In different to the U2730B-B the new version offers a power save function. For VPSM > 2 V (Pin 1) the power consumption in the analog part (gain-controlled amplifier and mixer and gain-controlled circuitry) is reduced by 80%. The VCO and the PLL is not influenced by the power-down mode. Gain-Control Circuitry The purpose of the gain-control circuitry is to measure the signal power, to compare it with a certain power level and to generate control voltages for the gain-controlled amplifier and mixer. An equivalent circuit of this functional block is shown in figure 6. In order to meet this functionality, the output signal of the buffer amplifier is weakly bandpass filtered (transition range about 60 MHz to 550 MHz), rectified, lowpass filtered and fed to a comparator whose threshold can be defined by an external resistor, RTH, at Pin TH. By varying the value of this resistor, a power threshold of about -33 dBm to -20 dBm can be selected. In order to achieve a good intermodulation ratio, it is recommended to keep the power threshold below -25 dBm. An appropriate application is shown in figure 3. Depending on the selection made by the comparator, a charge pump charges or discharges a capacitor which is applied to the Pin AGC. By varying this capacitor, different time constants of the AGC loop can be realized. The voltage arising at the Pin AGC is used to control the gain setting of the gain-controlled amplifier and mixer. The voltage at Pin AGC is in the range of 5.75 V for maximum gain and 0.3 V for minimum gain. This voltage can be use to control a dual-gate GaAs-FET in front of the U2730B-N to archieve an extended AGC-range. By applying an external voltage to the Pin AGC, the internal AGC loop can be overdriven. Frequency Synthesizer The frequency synthesizer block consists of reference oscillator, a reference divider, an LO divider in order to divide the frequency of the internal oscillator, a tri-state phase detector, a lock detector, a programmable charge pump, a loop filter amplifier, a control interface and a test interface. The control interface is accessed by three control Pins `CI', `SI1' and `SI2'. The test interface provides test signals which represent output signals of the reference and the LO divider. The purpose of this unit is to lock the frequency fVCO of the internal VCO on the frequency fref of the reference signal applied to the input Pin OSCB a phase-locked loop according to the following relation: fVCO = SF fref / SFref where: SF = 2464, SFref scaling factor of reference divider according to table 1 Rev.A1, 10-Jul-00 3 (13) Preliminary Information U2730B-N Table 1. Scaling factors of the reference frequency Voltage at Pin SI1 GND GND GND OPEN OPEN OPEN VCC VCC VCC Voltage at Pin SI2 OPEN VCC GND OPEN VCC GND OPEN VCC GND SFref 36 33 48 65 63 64 35 32 49 Reference Oscillator Frequency 18.432 MHz 24.576 MHz 32.768 MHz 17.920 MHZ 16.384 MHz Reference Oscillator An on-chip crystal oscillator generates the reference signal which is fed to the reference divider. By connecting a quartz crystal to the Pins OSCE, OSCB according to figure 10, this oscillator generates a highly stable reference signal. The U2731B (TEMIC Semiconductors one-chip front-end IC) offers the reference signal at Pin FREF. This reference signal (LC-filtered to suppress the harmonics) can be used to overdrive the oscillator. In this application (see figure 11) the reference signal has to be applied to the Pins OSCB and the Pin OSCE must be left open. Phase Comparator, Charge Pump and Loop Filter The tristate phase detector causes the charge pump to source or to sink current at the output Pin PD depending on the phase relation of its input signals which are provided by the reference and the RF divider respectively. By means of the control Pin CI, two different values of this current can be selected, and furthermore the chargepump current can be switched off. The input of the high-gain amplifier (output Pin CD) which is implemented in order to construct a loop filter, as shown in the application circuit, can be switched to GND by means of the control Pin CI (see table 2). In the application circuit figure 3, the loop filter is completed by connecting the Pins PD and CD by an appropriate RC network. Reference Divider Nine different scaling factors of the reference divider can be selected by different voltage settings at the input Pins SI1, SI2: 32, 33*, 35, 48, 49*, 65*, 64, 63*. The reference divider factors resulting in reference oscillator frequencies shown in table 1. *) These scaling factors result in an output frequency of the reference divider of 512 kHz. If harmonics of the Bd. 3 VCO are falling in the L-band reception band, this spurious can influence the AGC of U2730B-N. That could be a problem for small incomming signals. In this case it is possible to switch the reference divider from nref to nref+1. Lock Detector An internal lock detector checks if the phase difference of the input signals of the phase detector is smaller than approximately 250 ns in seven subsequent comparisons. If a phase lock is detected, the open collector output Pin PLCK is set to HIGH. It should be noted that the output current of this pin must be limited by external circuitry as it is not limited internally. If the voltage at the control Pin CI is chosen to be half the supply voltage, or if this control pin is left open, the lock-detector function is de-activated and the logical value of the PLCK output is undefined. Testinterface LO Divider The LO divider is operated at the fixed division ratio 2464. Assuming the settings described in the section `Reference divider', the oscillator's frequency is controlled to be 1261.568 MHz in locked state and the output frequency of the RF divider is 512 kHz. If the input control Pin CI is left open (high impedance state), a test signal which monitors the output frequency of the reference divider appears at the output Pin TI. In analogy to the reference divider a test signal which monitors the output frequency of the RF divider appears at the test interface output Pin TI if the input control Pin CI is connect to VCC/2. 4 (13) Rev.A1, 10-Jul-00 Preliminary Information U2730B-N Table 2. Control -interface (CI) settings CI GND Vs VCC/2 Open PD 200 A 300 A 0 A Connected to GND PLCK ok ok Undefined Undefined TI - - RF divider Reference divider Absolute Maximum Ratings Parameters Supply voltage RF input voltage Voltage at Pin AGC Voltage at Pin TH Input voltage at Pin TANK (internal oscillator overdriven) Current at IF output Reference input voltage (diff.) Control input voltage PLCK output current PLCK output voltage Junction temperature Storage temperature Pins 3, 9, 20 and 28 Pins 25 and 26 Pin 18 Pin 17 Pin 5 Pin 19 Pin 15 Pins 1, 2, 10 and 27 Pin 14 Pin 14 IIF OSCB CI, SI1, SI2, PD IPLCK VPLCK Tj Tstg 4.0 1 -0.3 to +9.5 0.5 -0.3 to +5.5 125 -40 to +125 mA Vpp V mA V C C Symbol VCC VRF VAGC VTH VTANK Value -0.3 to +9.5 750 0.5 to 6 -0.3 to +4.0 1 Unit V mVpp V V Vpp Operating Range Parameter Supply voltage Ambient temperature Pins 3, 9, 20 and 28 Symbol VCC Tamb Value 8.00 to 9.35 -40 to +85 Unit V C Thermal Resistance Parameter Junction ambient SSO28 (mod.) Symbol RthJA Value t.b.d. Unit K/W Electrical Characteristics Operating conditions: VCC = 8.5 V, Tamb = 25C, application circuit see figure 3, unless otherwise specified Parameter Supply current (max. gain) Supply current (min. gain) Supply current (power save mode) Rev.A1, 10-Jul-00 Test Conditions / Pins pRF = -60 dBm, VPSM < 0.5 V pRF = -10 dBm VPSM < 0.5 V pRF = -10 dBm VPSM > 2 V Symbol IS,MAX IS,MIN IS,PD Min. Typ. 40 41 20 Max. 48 50 24 Unit mA mA mA 5 (13) Preliminary Information U2730B-N Electrical Characteristics (continued) Operating conditions: VCC = 8.5 V, Tamb = 25C, application circuit see figure 3, unless otherwise specified Parameter Amplifier mixer Maximum conversion gain Minimum conversion gain AGC range Third order 2 tone intermodulation ratio DSB noise figure (50- system) RF input Frequency range Maximum input power Input impedance IF output Frequency range Output impedance Voltage standing wave ratio Gain control Threshold adjustment Charge pump current External resistor pRF = -10 dBm Vagc = 3.5 V pRF = -60 dBm Vagc = 3.5 V Minimum gain control voltage Maximum gain control voltage VCO Frequency Phase noise Minimum input power Maximum input power Frequency synthesizer RF divide factor Reference divide factor SI1 = GND, SI2 = GND SI1 = GND, SI2 = VCC SI1 = GND, SI2 = open SI1 = VCC, SI2 = GND SI1 = VCC, SI2 = VCC SI1 = VCC, SI2 = open SI1 = open, SI2 = GND SI1 = open, SI2 = VCC SI1 = open, SI2 = open SF SFref 2464 48 33 36 49 32 35 64 63 62 Rev.A1, 10-Jul-00 1 kHz distance VCO overdriven, application circuit see figure 6 pRF = -10 dBm pRF = -60 dBm Pin 5 fLO L1kHz pLO,MIN pLO,MAX 1000 1261.568 Test Conditions / Pins Pin 26 19 pRF = -60 dBm pRF = -15 dBm pRF1 + pRF2 = -10 dBm pRF1 + pRF2 = -15 dBm Maximum gain Minimum gain Pin 26 Symbol gc,max gc,min Dgc dim3 NF Min. 20 28 30 35 Typ. 24 -8 32 35 40 10 30 Max. Unit dB dB dB dB dB dB dB fin,RF dim3 20 dB Pin 19 fout,IF Zout,IF VSWRIF Pin 17 Pin 18 RTH ICP,P ICP,N Pin 18 Pin 18 VAGCmin VAGCmax pin,max,RF Zin,RF 1400 -6 200 || 1 150 50 2.0 100 75 -125 100 -100 0.1 5.5 5.75 1550 MHz dBm || pF 250 MHz k 125 -75 0.6 A A V V 1500 MHz dBc/Hz dBm dBm -75 -11 -5 6 (13) Preliminary Information U2730B-N Electrical Characteristics (continued) Operating conditions: VCC = 8.5 V, Tamb = 25C, application circuit see figure 3, unless otherwise specified Parameters Input frequency range Input sensitivity Maximum input signal Input impedance Phase detector Charge-pump current Pin CI connected to GND Pin 13 Pin CI connected to VCC Pin CI connected to VCC/2 Output voltage PD Internal reference frequency Typical tuning voltage range Lock indication Leakage current Saturation voltage Control inputs SI Input voltage PLCK Pin 14 VPLCK = 5.5 V IPLCK = 0.25 mA Pins 2 and 27 Pin connected to GND Pin open Pin connected to VCC Control input CI Input voltage Pin 10 Pin connected to GND Pin connected to VCC/2 Pin open Pin connected to VCC Test interface Reference test frequency LO test frequency Voltage swing TI Pin 11 ftest,ref ftest,LO Vsw 512 512 400 kHz kHz mVpp Pin CI open Pin CI = VCC/2 Rload 1 M, Cload 15 pF, Pin CI open or VCC/2 PSM PSM active Pin 1 VPSM VPSM 2.0 0.6 V V PSM not active VL VM Vopen VH 0.9 0 0.5 open 1 V 0.1 V V VL VM VH 0.9 0 open 1 V 0.1 V IPLCK VPLCK,sat 10 0.5 A V Pin 12 Pin CI open Pin 13 IPD2 IPD1 IPD1,tri VPD fPD Vtune 0.3 512 5 160 240 200 300 240 360 100 0.3 A A nA V kHz V Single-ended Pin 15 Pin 15 Test Conditions / Pins Symbol fref Vrefs Vrefmax Zref 300 2.7k || 2.5 Min. 5 Typ. Max. 50 30 Unit MHz mVrms mVrms kW || pF Power-save mode Example: reference divider factor = 35, fREF = 17.92 MHz, charge-pump current = 200 mA Rev.A1, 10-Jul-00 7 (13) Preliminary Information U2730B-N Gain Control Charateristics Operating conditions: VCC = 8.5 V, Tamb = 27C, fRF = 1490 MHz, FLO = 1261.568 MHz -10 -15 vAGC ( V ) pIF ( dBm) -20 -25 Rth=100 kW -30 -35 -40 -60 14851 6 5 Rth=100 kW 4 3 2 1 0 -60 14852 -50 -40 -30 -20 pRF ( dBm ) -10 0 -50 -40 -30 -20 pRF ( dBm ) -10 0 Figure 3. IF output power (Pin 19) Figure 4. Gain control voltage (Pin 11) Phase-Noise Performance Measurement conditions: Values aquired at Pin 19 with HP 70000 spectrum analyzer. RF input (Pin 26) is blocked with 100 pF to GND. A low phase-noise signal generator (Marconi 2042) was taken as PLL reference. RL -29.29 dBm ATTEN 10 dB 10.00 dB/DIV < -75 dBc/Hz Center 1.261 568 GHz RB 100 Hz VB 100 Hz Span 50.00 kHz ST 15.00 sec Figure 5. Phase noise performance Operating conditions: fREF = 17.92 MHz, -10dB, IPD = 200A 8 (13) Rev.A1, 10-Jul-00 Preliminary Information U2730B-N Equivalent Circuits Gain- controlled mixer Gain- controlled amplifier VRef1 550MHz IF output 60MHz VRef2 AGC TH Rth 15001 Figure 6. AGC contol circuit VTune 47k BBY51 VCC 1.8p 15p Resonator 1p VREF TANK 100p Resonator: Ceramic coaxial resonator Murata 3 x 3 mm, 1.6 GHz DRR030 KE1R600TC Figure 7. VCO circuit Rev.A1, 10-Jul-00 9 (13) Preliminary Information U2730B-N Application Circuit VAGC 3.3uF 8.5 V 100pF 100pF RF 8.5 V 100pF IF 1nF 100K 18pF 100 pF 1nF 33pF Quartz crystal 10nF 100pF 10nF 68pF 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC4 SI1 RF NRF GND GND GND GND VCC3 IF AGC TH OSCE OSCB U2730B-N PSM 1 SI2 VCC1VREF TANK GND GND GND VCC2 CI 2 3 4 5 6 7 8 9 10 TI 11 CD 12 PD PLCK 13 14 Power save 100pF 1pF 10nF 10nF *100pF 56K 5V Lock indication 100pF 100pF 8.5 V 8.5 V 1.8pF 1nF 47K 1nF 15pF 1K *3.3 1K *3.3 nF * optional D1 nF Figure 8. Application circuit 10 (13) Rev.A1, 10-Jul-00 Preliminary Information U2730B-N Application Circuit for External LO Signal With an external LO signal it is possible to overdrive the VCO. In this case, the internal VCO acts as an LO buffer. ext. LO signal (50 signal gen.) PLO = -10dBm 50 TANK 100p 470nH VREF 1n Figure 9. Application circuit for external LO signal 68pF OSCB Reference devider 33pF OSCE Quartz crystal 18pF Figure 10. Reference oscillator operation OSCB Reference signal L1 C1 OSCE Reference devider Figure 11. Reference oscillator overdriven Rev.A1, 10-Jul-00 11 (13) Preliminary Information U2730B-N Package Information Package SSO28 Dimensions in mm 9.10 9.01 5.7 5.3 4.5 4.3 1.30 0.25 0.65 8.45 28 15 0.15 0.05 6.6 6.3 0.15 technical drawings according to DIN specifications 13018 1 14 12 (13) Rev.A1, 10-Jul-00 Preliminary Information U2730B-N Ozone Depleting Substances Policy Statement It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. 3. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify TEMIC Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.temic-semi.com TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423 Rev.A1, 10-Jul-00 13 (13) Preliminary Information |
Price & Availability of U2730B-N
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |